1. Field of the Invention
The present invention relates to a clock generation circuit and a method for generating a clock signal. More particularly, the present invention relates to a duty cycle correction circuit, a clock generation circuit using the same, and a method for generating clock signals with the use thereof.
2. Description of the Related Art
Semiconductor devices which employ clock generation circuits often include phase lock loop (PLL) circuits or delay lock loop (DLL) circuits. A conventional PLL comprises a voltage controlled oscillator (VCO), which generates relatively higher frequency internal clock signals, and a duty cycle correction circuit (DCC), which comprises at least a pair of amplification part and corresponding charge pump. On the other hand, a conventional DLL comprises a voltage controlled delay line (VCDL) and a DCC, which likewise comprises at least a pair of amplification part and corresponding charge pump.
Referring to FIG. 1, a conventional PLL circuit 100 includes a phase detector (PD) 110, a charge pump (CP) 120, a loop filter (LP) 130, a voltage controlled oscillator (VCO) 140, a divider (DIV) 160 and a duty cycle correction (DCC) circuit 150.
During operation, PD 110 generates a control signal in response to a phase difference between an external clock signal (INS) and a feedback clock signal (FEEDS) and provides the control signal to CP 120. The control signal comprises an UP signal and a DN signal (not shown). When the phase of INS leads that of a feedback clock signal, PD 110 is activated and generates an activated UP signal. In contrast, when the phase of the INS lags than that of the FEEDS, PD 110 generates an activated DN signal. CP 120 and LP 130 increase the level of control voltage (VC) in response to the activated UP signal, and decrease the level of VC in response to the activated DN signal. The control voltage is input to VCO 140.
VCO 140 generates two intermediate clock signals CLK and CLKB which are received by DCC 150. The phase difference between CLK and CLKB is about 180 degrees. DCC eliminates a duty cycle error existing in each of the intermediate clock signals CLK and CLKB and generates first internal clock signals CCLKB and CCLK which keep a normal duty cycle (50%:50%). The phase difference between CCLKB and CCLK is also about 180 degrees.
DIV 160 receives one of the first internal clock signals (which is CCLK in the example of FIG. 1), and then outputs the divided clock signal FEEDS, whose frequency equals the frequency of INS. That is, in order to acquire first internal clock signals CCLKB and CCLK having a higher frequency than that of external clock signal INS, DIV 160 is provided in the PLL. On the other hand, when a PLL doesn't have a divider, such as DIV 160, the frequency of first internal clock signals CCLKB, CCLK equals the frequency of external clock INS.
Referring to FIG. 2, a conventional DLL circuit 200 includes VCDL 240, rather than VCO 140 of PLL 100, as well as phase detector (PD) 210, a charge pump (CP) 220, a loop filter (LP) 230 and a duty cycle correction (DCC) circuit 250.
During operation, VCDL 240 generates intermediate clock signals CLKB, CLK which are delayed by a predetermined time from an external clock signal INS, in response to an output signal of a charge pump CP 220 and LP 230 (which is generally composed of a low pass filter). Then, DCC 250 generates first internal clock signals CCLKB, CCLK which keep normal duty cycle after eliminating a duty cycle error which may exist in the each of intermediate clock signals CLK, CLKB.
Referring to FIG. 3, a conventional DCC circuit 150,250 is described in more detail as follows. DCC 150,250 may receive differential clock signals CLK and CLKB having a phase difference of about 180 degrees, as shown in FIG. 3 (which will be described further with reference to FIG. 4), and may also receive a single-ended clock signal (which will be described further with reference to FIG. 5). In the case of differential clock signals, the duty cycle errors of the intermediate clock signals CLK, CLKB are corrected in response to control signals VC,VCB generated from a charge pump CP 320 of the DCC circuit. CP 320 adjusts the voltage value of the control signals VC, VCB in response to signals CCLK,CCLKB so that an amplification part (AP) 310 adjusts the duty cycle of signals CLK,CLKB according to the voltage value of each of VC,VCB to output first internal clock signals CCLK,CCLKB keeping normal duty cycle (50%:50%).
Referring to FIG. 12a, when intermediate clock signals CLK/CLKB do not have a duty cycle error, first internal clock signals CCLK/CCLKB also do not have a duty cycle error. Thus, the average voltage of control signal VC for one clock period remains constant at every interval of all clock periods.
Referring to FIG. 13a, when intermediate clock signals CLK/CLKB have a duty cycle error, first internal clock signals CCLK/CCLKB also have a duty cycle error. Accordingly, CP 320 of the DCC circuit 150,250 operates to adjust the voltage level of control signal VC to control AP 310 to correct the duty cycle error of the clock signals. As shown, the average voltage value of a control signal VC for one clock period differs from every interval until CCLK/CCLKB are restored to normal duty cycle by operation of the DCC circuit.
Referring to FIG. 4, VCO 410 outputs two pairs of differential clock signals CLK1/CLKB1, CLK2/CLKB2. In this case, DCC 400 comprises two charge pumps (CP) 430a,430b arranged in a one to one correspondence with amplification parts (AP) 425a,425b, as shown by blocks 420a and 420b, to correct duty cycle errors of each of the two pairs of differential clock signals. While FIG. 4 illustrates a relationship between VCO 410 and DCC 400 in a PLL circuit, one of ordinary skill in the art will appreciate that a similar arrangement between a VCDL and a DCC would exist in a DLL circuit where a VCDL would be used in place of the VCO 410.
Referring to FIG. 5, VCO 510 outputs four single-ended clock signals CLK1,CLK2,CLK3,CLK4. In this case, DCC 500 comprises four charge pumps (CP) 530a,530b,530c,530d arranged in a one to one correspondence with amplification parts (AP) 425a,425b,425c,425d as shown by blocks 520a, 520b, 520c and 520d, to correct duty cycle errors of each of the four single-ended clock signals. The duty cycle errors of the intermediate clock signals CLK1,CLK2,CLK3,CLK4 are corrected in response to control signals VC1,VC2,VC3,VC4 generated from CPs 530a,530b,530c,530d, respectively, which adjust the voltage values of the control signals VC1,VC2,VC3,VC4 in response to signals CCLK1,CCLK2,CCLK3,CCLK4 so that APs 425a,425b,425c,425d adjust the duty cycle of signals CLK1,CLK2,CLK3,CLK4 according to the voltage value of each of VC1,VC2,VC3,VC4, respectively, to output duty cycle corrected first internal clock signals CCLK1,CCLK2,CCLK3,CCLK4.
As in the case of FIG. 4, while FIG. 5 illustrates a relationship between VCO 510 and DCC 500 in a PLL circuit, one of ordinary skill in the art will appreciate that a similar arrangement between a VCDL and a DCC would exist in a DLL circuit where a VCDL would be used in place of the VCO 510.
As can be seen from the foregoing description, in conventional clock generation circuits, a charge pump for duty cycle correction is arranged in correspondence with each of the amplification parts which receives intermediate clock signals and generates first internal clock signals. The plurality of charge pumps required in duty cycle correction circuits of conventional semiconductor devices leads to high power consumption and requires a large chip area.